can anyone tell me the difference between pipelined bus and depipelined bus?and i have uploaded two screen shot of both so what does that arrow from mclk to a[31:0] indicates?

Hi ineev,

I think in these diagrams the second is described as "de-pipelined" because when the data transfer occurs the address value is still valid on the bus, similar to what you would have for an SRAM access, so a simpler timing.

However this "de-pipelined" timing reduces the time available for the slave to decode the address value and work out which element in the slave is being accessed, so the "pipelined" timing in the first diagram shows the address valid a half MCLK cycle earlier, but not valid when the data transfer occurs.

This "pipelined" timing is better for DRAM type accesses where knowing the address in advance of the data transfer allows you to determine which element is to be accessed, selecting the separate row and column in the memory array before the data arrives.

A pipelined bus gives as much advanced notice of the transfer control signals, hopefully reducing any wait states needed by the slave while it works out what data transfer is required, but it does mean that you might also then need to register the control signals in the slave if you also need them to be valid at the time the data transfer occurs.

So the arrow in each diagram shows the MCLK edge that was used by the ARM7TDMI processor to drive out the A[31:0] value, MCLK rising when APE is high (the pipelined timing), and MCLK falling when APE is low (the "de-pipelined" timing).

Hope that helps answer this question.

JD

thank you for such wonderful  answer,

you said that  the arrow in each diagram shows the MCLK edge that was used by the ARM7TDMI processor to drive out the A[31:0] value, MCLK rising when APE is high (the pipelined timing), and MCLK falling when APE is low (the "de-pipelined" timing).

but in both diagram A[31:0] is being latched after edges(i.e on either high level or low level of clock),so can you tell me why?

and in articles of arm7, it is said that in arm7tdmi, both negative edge and positive edge of MCLK are  used so how it is used?

Inside the ARM7TDMI it will be generating its internal address value on the MCLK rising edges, so what you see in the "pipelined addresses" diagram.

However if you want the "depipelined addresses" timing, APE will select between the internal address timing when APE=1, and a version of the address either registered on MCLK rising edges or latched (open on MCLK low) when APE=0.

The "depipelined" timing would be offered to simplify interfacing with static RAM type slaves where address and data need to be valid at the same time, but the native "pipelined" timing should result in fewer wait states in higher clock speed systems because the address is known before when the slave needs to perform a data transfer. So APE allows you to select the timing best suited to your design.

As you can see in the "pipelined" timing diagram, nMREQ and SEQ are driven following MCLK falling edges, then ADDR is driven following MCLK rising edges, and the data transfer completes on MCLK falling edges, so both edges of MCLK need to be used by the system (your slaves need to know which clock edge to use to sample each input, and when to drive outputs so that they will be valid when the ARM7TDMI is sampling them). Not sure if that answers your "how is it used" question.

Using both edges of MCLK is not readily supported by synthesis tools and cell libraries, and can lead to critical timing paths, so more modern bus protocols only use rising edges of the clock (AHB, AXI and so on).

JD

Hi ineev,

The ARM7TDMI TRM would be the document I'd expect you should refer to for details of how that core works, but as your first question was quoting diagrams from that TRM I guess you already have it.

So what sort of areas do you need more info on that are not covered by the ARM7TDMI's TRM ?

JD

thank you for helping me.

i want get knowledge on arm7tdmi core and want to learn in depth like how core is interfaced with memory in SoC and memory mapping and memory remapping concept in one of the arm7 based SoC named lpc2148 so that i can come to know what mechanism they have used in memory mapping and remapping and the role of SoC and CORE in Remapping the memory so that is why i have started from scratch (i.e bus timing and all).

actually i am programmer (c, assembly and linux kernel) and what to learn ARM core in Depth so if you can help me on topics i have told in above paragraph so it would be very helpful to me.

Hi ineev,

Sorry but I've never used that device, so cannot say how the ARM7TDMI core has been integrated with the rest of the "lpc2148" system.

If nobody on this forum can help you, it might be better approaching the vendor of this device, which I think might be NXP based on what I am seeing when searching for this part.

I'm also seeing that it is based on the ARM7TDMI-S rather than the ARM7TDMI, so different signal timings because it is a synthesisable core.

JD