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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3579 Questions
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  • Answered

    Questions about Write Interleaving Exclusion in AXI4 Protocol 0

    • AXI3
    • AXI
    • AXI4
    1980 views
    2 replies
    Latest over 1 year ago
    by Cheng En Lee
  • Not Answered

    APU slave core issue. 0

    1417 views
    3 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    TrustZone preemption 0

    1331 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Cycle Number For 1024 Complex FFT on R52+ Neon 0

    1001 views
    1 reply
    Latest over 1 year ago
    by Alexander Tessarolo
  • Suggested Answer

    Cortex-R52+: measure the number of executed instructions 0

    • executed instructions
    • pmu
    • instruction number
    • Cortex-R52+
    2096 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    A53 core 1,2 and 3 crash. 0

    607 views
    0 replies
    Started over 1 year ago
    by Diptendu
  • Answered

    Cortex-R52 exception priority 0

    • Exception Handling
    • Cortex-R52
    1391 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Porting simple code to M4 to A7 0

    • Cortex-A7
    • Debugging
    • Cortex-M4
    1782 views
    3 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    M55 CPU - cacheable region 0

    • M55 cpu
    753 views
    0 replies
    Started over 1 year ago
    by GMH
  • Not Answered

    Cortex-R8 QoS enable limitation 0

    • R8
    • cortex-r8
    640 views
    0 replies
    Started over 1 year ago
    by junhao.wang
  • Not Answered

    Why is the ACELS interface of the R82 prohibited from non-modifiable bursts? 0

    • R82
    662 views
    0 replies
    Started over 1 year ago
    by Chen Haoming
  • Suggested Answer

    Cortex-m7 Cache prefetching 0

    • Cache Controllers
    1486 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    Is there possibility to achieve unsupervised AMP with armv8-a arch (cortex-a53)? 0

    • Armv8-A
    755 views
    0 replies
    Started over 1 year ago
    by Soumya Tripathy
  • Suggested Answer

    Where can I find example code for an M33 HardFault_Handler with core register dump? 0

    1624 views
    1 reply
    Latest over 1 year ago
    by tobermory
  • Suggested Answer

    Exception return for Cortex-M7 0

    • Exception Handling
    • Interrupt Handling
    • Cortex-M7
    2529 views
    4 replies
    Latest over 1 year ago
    by tobermory
  • Not Answered

    axi stream synchronous reset and Questa QVIP assertion checker 0

    • axi stream protocol
    1184 views
    1 reply
    Latest over 1 year ago
    by Annie
  • Not Answered

    IPXACT for Cortex A72, A78 and others 0

    • ipxact
    786 views
    0 replies
    Started over 1 year ago
    by Nathan Krueger
  • Not Answered

    Add custom CPU features 0

    • CPU Architecture
    • Hypervisor
    710 views
    0 replies
    Started over 1 year ago
    by Mingwang Li
  • Not Answered

    regions configured in the TZC-400 and the source from where the AXI-low power signals are coming to TZC-400 0

    1350 views
    1 reply
    Latest over 1 year ago
    by sreeja vasi
  • Not Answered

    Cortex-M33_TZ FuSa and Security assessment report. 0

    • Fusa
    • TrustZone for Armv8-M
    • Cortex-M33
    658 views
    0 replies
    Started over 1 year ago
    by Vishal Rana
<>
Topics being discussed in this forum
  • AArch64
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  • Arm Assembly Language (ASM)
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