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About unsupported exclusive or atomic access issue

Wesley Hwang

Hi,

I am working on FPGA platform having 1 cluster of A725 with 3 cores. I am running QNX on cluster-0/core-0 without HYP. While QNX kernel booting, I am getting data abort exception 0x96000035 (unsupported exclusive or atomic access) when executing a specific instruction, CASAL, in the following process and setting. 

[Steps]

  1. Get result 0b0010 from CPU register ID_AA64ISAR0_EL1 Atomic, bits [23:20] <- LSE support
  2. MMU enable before kernel start in EL1
  3. Execute instruction 'casal w1,w2,[x0]' 
  4. Get error code '0x96000035' in ESR_EL1 register

            bit[5:0] 0b110101 means IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access).

In step 4, the ESR_EL1 shows that an unsupported exception is triggered when executing the casal instruction, but in step 1, the capability retrieved from the CPU register indicates that it is supported. Two information are conflict. After attempting to run QNX without LSE flag rising, it runs normally.

Can anybody give hint on the issue?

Parents
  • 0 in reply to Martin Weidmann

    Thank you for your response. SCTLR_EL1.C is enabled, and the complete setting is 0x34D5D99D. I tried to analyze the memory address read by the CASAL instruction as follows:

    1. The CASAL instruction is as follows
      1. casal w1,w2,[x0]
    2. The location stored in X0 is as follows
      1. X0  0xFFFFFF80600F8E6C
    3. The memory location's attributes in the page table are as follows
      1. Logical PHYSICAL SEC SIZE PERMISSION GLB SHR ACCESS
        FFFFFF80600CB000 -- FFFFFF80600CFFFF 4 KB
        FFFFFF80600D0000 -- FFFFFF8060105FFF 00000000B00CB000 -- 00000000B0100FFF  ns 4 KB readwrite  notexec yes no I:wr-back/rwa O:wr-back/rwa
        FFFFFF8060106000 -- FFFFFF80821FFFFF 4 KB

    From step 3, it appears that the cache mechanism is being used, but it still triggers an exception. Do you have any ideas?

Reply
  • 0 in reply to Martin Weidmann

    Thank you for your response. SCTLR_EL1.C is enabled, and the complete setting is 0x34D5D99D. I tried to analyze the memory address read by the CASAL instruction as follows:

    1. The CASAL instruction is as follows
      1. casal w1,w2,[x0]
    2. The location stored in X0 is as follows
      1. X0  0xFFFFFF80600F8E6C
    3. The memory location's attributes in the page table are as follows
      1. Logical PHYSICAL SEC SIZE PERMISSION GLB SHR ACCESS
        FFFFFF80600CB000 -- FFFFFF80600CFFFF 4 KB
        FFFFFF80600D0000 -- FFFFFF8060105FFF 00000000B00CB000 -- 00000000B0100FFF  ns 4 KB readwrite  notexec yes no I:wr-back/rwa O:wr-back/rwa
        FFFFFF8060106000 -- FFFFFF80821FFFFF 4 KB

    From step 3, it appears that the cache mechanism is being used, but it still triggers an exception. Do you have any ideas?

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