Good day.
I am reading the reference manual for the Cortex-M4 processor and I see that this processor uses the AMBA AHB-Lite 3 bus architecture version. I open the AMBA AHB-Lite 3 specification and do not see a description of the MEMATTR signals, which the processor uses to encode information about the memory type when accessing it - normal, device, or strictly ordered. Why is there no description of these signals in the specification? If these are "out-of-band" signals, then I do not see in the AMBA AHB-Lite 3 description the admissibility of expanding the bus signals (maybe I did not look carefully?).
AHB-lite was a simplification of the original AHB protocol (no additional functionality), so although Cortex-M4 came out at around the same time as AHB-lite, any additional information signals the Cortex-M4 would want to drive were not supported by the AHB (and thus the AHB-lite) protocol, and so would need to be considered "side-band" signals not officially supported by the AHB-lite specification.
Originally the AMBA spec writers would not want users to add any side-band signals to the protocol as that would immediately make any interface non-standard, and so defeating the purpose of having a bus "STANDARD" in the first place. Hence it not suggesting you can add "out-of-band" signals.
The AHB protocols tried to avoid the use of "user" defined type signals, again because they immediately make an interface non-standard if two components have different uses of the added user-defined controls, but the latest AHB5 specification has now allowed you to add HAUSER, HWUSER and HRUSER ports (although still with a recommendation that you do not use them), so these could be used to pass the MEMATTR signals.
And you sometimes do see AHB and AHB-lite based designs with non-standard additional "sideband" signals on their interfaces. They just are not covered by the protocol, and won't then be immediately compatible with other AHB or AHB-lite compatible designs.