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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3611 Questions
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  • Not Answered

    Need help to choose MCU 0

    647 views
    0 replies
    Started over 1 year ago
    by Sharath HS
  • Not Answered

    Linker errors compiling for Cortex-M33 0

    • compiler
    • Cortex-M3
    • GNU Arm
    • Cortex-M33
    • Linking Error
    1156 views
    0 replies
    Started over 1 year ago
    by Jorg Wieme
  • Not Answered

    ARM SBSA sbsa_gwdt watchdog timer driver Pretimeout feature 0

    1381 views
    1 reply
    Latest over 1 year ago
    by Akshay Dharmapuri
  • Answered

    [APB5]What is this limitation about three logic levels available in timing allowances for generating parity bit? 0

    1210 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 Unaligned transfer WRITEs and READs 0

    • AMBA
    • AXI4
    • unaligned
    3483 views
    3 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 unaligned transfer +1

    3816 views
    4 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    M55 PMU cycle counter returning 0. 0

    • Cortex-M55
    • Armv8.1-M
    • pmu
    • cycle count
    • Cortex-M
    • Armv8-M
    849 views
    0 replies
    Started over 1 year ago
    by Karthik Kumar G R
  • Not Answered

    ETE Instruction Trace Configuration 0

    • Debug and Trace
    668 views
    0 replies
    Started over 1 year ago
    by Lauren Ho
  • Not Answered

    Is the SYST_CVR (0xE000E018) register accessible in USER mode ? 0

    1188 views
    2 replies
    Latest over 1 year ago
    by Hicham Boutlalek
  • Suggested Answer

    TxnID in AMBA CHI Chip-to-Chip 0

    • CHI
    1839 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Configuration Control Register (CCR). 0

    810 views
    0 replies
    Started over 1 year ago
    by Pragathi Simha
  • Not Answered

    Can Cortex-M33 MCUs enable SAU and MPU_NS simultaneously? 0

    • mpu
    • Cortex-M
    • Cortex-M33
    • Armv8-M
    • SAU
    682 views
    0 replies
    Started over 1 year ago
    by kiko
  • Answered

    Exception return issues with Cortex-M3 on STM32F103C8T6 0

    • Exception Handling
    • Interrupt Handling
    • stm32f103
    • Cortex-M3
    • STM32
    • Interrupt
    2976 views
    2 replies
    Latest over 1 year ago
    by Nancen Li
  • Suggested Answer

    Socrates for SSE-315 subsystem 0

    1785 views
    2 replies
    Latest over 1 year ago
    by Ian J Arm Employee Badge
  • Suggested Answer

    gic-600 interconnection through AXI-Stream interface 0

    • gic
    1852 views
    2 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    What Causes Program Performance to Decline Despite an Increase in Cache Hit Rate? 0

    • Cortex-A76
    788 views
    0 replies
    Started over 1 year ago
    by y say
  • Not Answered

    ASIC AES in ARM CPU, on data bus 0

    • Security
    670 views
    0 replies
    Started over 1 year ago
    by Teddy Rahbe
  • Answered

    DVM operations in ARM ACE5 0

    3935 views
    7 replies
    Latest over 1 year ago
    by Rohith Jonnabhatla
  • Suggested Answer

    AXI Write Interleaving 0

    • AMBA
    • AXI3
    • AXI
    • AXI4
    2092 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Invisible system cache 0

    2453 views
    4 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
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