Need for DSB and ISB for interrupt pending to take immediate action.

For Cortex-M processors I can see ARM recommends using both __DSB and __ISB memory barriers after pending an interrupt (e.g. PendSV) to guarantee it is taken immediately. 
In the same document (ARM memory barriers app note), it is mentioned that these are only architectural requirements.

So for e.g. Cortex-M7, are both barriers necessary? Or do I just need __ISB? FreeRTOS uses both when a task yields. This article however uses only __ISB (https://interrupt.memfault.com/blog/arm-cortex-m-exceptions-and-nvic). I have also seen implementations only use DSB.

So which is correct? The ARM app note mentions that NVIC writes already exhibit DSB barrier behavior by themselves but this is only between strongly ordered and device memory, not normal memory (e.g. writing a variable on the stack).