I'm reading APB5.0 specs and while reading the parity checking chapter I encountered a ceratin limitations in parity bit. The limitation is that parity check assumes that three logic levels are available in the timing allowance for generating each parity bit? So what does it actually mean?
While researching the three logic levels are-Setup time,hold time,propogation time. Is it related to this?
The 3 levels of logic refer to the simple logic needed to calculate a parity value for an 8 bit signal. If you gate together 2 bits of the 8-bit signal at a time, you can calculate a parity value after 3 levels of combinatorial logic (4 pairs in the first level, 2 pairs in the second level, and one pair for the 3rd level).
7 \___ 6 / \___ 5 \___/ \ 4 / \___ 3 \___ / 2 / \___/ 1 \___/ 0 /
So with a very shallow combinatorial structure you can calculate a parity value for that 8-bit signal easily within the timing budget for the signal's propagation from source to destination.
If you had more levels of combinatorial logic (trying to cover signals wider than 8-bits with one parity bit) you could easily start to impact on the timing budget for this path, hence 8 signal bits per parity bit being the described parity implementation.