APB : How does Single Master and Multiple Slaves Work in APB?

I am currently working on the development of an APB (Advanced Peripheral Bus) VIP with a Single Master and Multiple Slaves. I have a query regarding how the interconnect determines which slave to select when the master communicates with a specific slave. Specifically:

  1. Slave Selection Mechanism:

    • Does the master use the PSEL signal (e.g., PSEL[1:0] for 4 slaves) to directly indicate which slave to communicate with?
    • Or is it based on address mapping, where specific address ranges (e.g., 0-1023 bytes for Slave 1, 1024-2047 bytes for Slave 2) are predefined, and the master sets PSEL as a single bit while the interconnect maps the address to the appropriate slave?
  2. Interconnect and Slave Behavior:

    How does the interconnect handle decoding and routing to the appropriate slave?

    Additionally, how should the slave behave in such a system, particularly with respect to decoding and responding to transactions?

Could you provide a detailed explanation of the overall flow of communication in such a Single Master to Multiple Slaves APB system?


Also,does APB have any boundary limitations, similar to the 4KB boundary size constraint in AXI?

  • An APB target is selected by the PSEL signal being high. Only 1 PSEL signal will be high at any one time on a multi-target APB system.

    The APB protocol describes PSELx as a single bit, so you wouldn't encode your 4 target select lines as PSEL[1:0] as this then means each APB target needs to decode the encode PSEL "bus".

    PSEL is generated based on address decoding of an active transfer request, so if the APB bridge is connected to an AHB driver this decoding will drive a PSEL output high (based on a decode of HADDR) when HTRANS was NONSEQ or SEQ, and if the connected protocol is AXI then PSEL will be high when an xVALID/xREADY handshake completes targeting this bridge (with AxADDR giving the address to decode to generate a PSEL output).

    And finally APB doesn't have any address boundary restrictions because it doesn't support bursts, so any transfer sequence is just a series of individual transfers.

    For the "Interconnect" questions I think that is all very implementation specific. The interconnect could generate individual APB ports for each target APB device so you don't have to consider external routing or decoding, or it could produce a single APB "Requester" interface with one or more PSEL lines and then require the user to add external logic to generate individual PSEL lines (so a simple PADDR decoder), and to route the APB target responses (PRDATA, PSLVERR, PREADY) from the active target.

    I don't know if that answers all your questions, but if you are designing a VIP I can't be too implementation specific.