Cortex A9 Boot operation Sequence

We're developing a proprietary RTOS using several of the cores in a Cortex A9MP processor. We've already run the OS on a single core, and now want to add additional cores. My main question is concerning the cache and MMU initialization for the primary core vs the secondary cores. The sequence for the primary core is:

1. Initialization of memory and stacks
2. Initialize the GICD and GICC
3. Disable L2 cache
4. Invalidate L1 dcache
5. Invalidate L1 icache
6. Invalidate the TLB
7. Enable dcache prefetch
8. Enable branch prediction
9. Allocate memory for the MMU table
10. Write the address of the MMU table into TTBR0
11. Create the basic entries in the MMU table
12. Set client mode for all domains (DACR)
13. Set SMP bit
14. Enable the SCU
15. DSB
16. ISB
17. Enable the dcache
18. Enable the L2 cache
19. Enable the icache
20. Enable the MMU in sctlr

This is the basic sequence. After this, core 0 is up and running with both L1 and L2 caches enabled. So my question is can I now enable core 1 with the L2 cache enabled, or do I need to bring it up and functional, and then enable the L2 cache? The MMU is set up with flat mapping, and the memory space for each additional core is set to shared so that core 0 can write the OS into it. Each core has the SMP bit set. The MMU table is accessible to all the cores.