Hi
The R52+ CPU goes to data abort and the DFSR is 0xA11 (asynchronous external abort for write access). I saw some tickets indicating that cache could lead to asynchronous abort.
I wonder whether the write-through cache can generate such asynchronous external abort ?
BR, Grace
I don't know specifically for the Cortex-R52, but in general yes - you could see async aborts with write-through caches.
I suspect the problem you've read about is the write-back of dirty data on cache line eviction. That specific problem doesn't happen with write-through caches, as there are no dirty lines. However, you can get a similar problem whenever the write is buffered in someway. That is, when the store instruction is permitted to be retired before he write it caused has fully happened in the memory system. If a buffered store ultimately leads to an external abort, you've lost the relationship to the instruction that caused the write making it asynchronous.
Hi Martin
We tried disabling I cache and D cache and the issue still happened. I think the issue is not due to the cache. Is there any possible cause ?
Cacheable accesses aren't the only place you'll get buffered writes, and buffered writes aren't the only possible cause of async external aborts.
I'd approach it from a different angle - you know there is an external abort but not what is causing it. So the question is: what could have caused it? As in, given the memory system of your device, what are the potential things that would result in an external abort. My suspicion is that you've not got the MPU set up correctly for the memory system of your device resulting in an access being generated that the memory system can't handle. So if it was me, I'd be checking: