Hi,
Is there any reason that a Cortex-R5F SoC can hang upon reception of an IRQ (not even enter any exception vector)?
I was configuring a TTC timer on Xilinx UltraScale+ SoC, which includes ARM cores including Cortex-A53 and Cortex-R5F. The Cortex-A core is currently not in use. During configuration of the TTC timer IRQ, which was supposed to be routed to the R5 core, I found that R5 core hangs upon reception of the IRQ.
To verify that it is indeed the TTC IRQ that hangs the R5 core, I've tried the following:
With these observations, I think that a successful delivery of an IRQ can hang the R5 core. But I have no idea why 1) there has no exception taken upon/prior to the hang; 2) the IRQ cannot be handled properly.
Surprisingly, in JTAG mode, the same code works like a charm, which makes me guessing that JTAG somehow overrides, for example, the GIC.
Does anyone have an idea for this?
As a side note, the R5 core was in SVC mode prior to receiving the IRQ, I'm currently not sure whether receiving IRQ under SVC mode can hang the R5 core.
Thanks!
Answering the side note: switching to System mode doesn't make any changes, the R5 core still hangs upon IRQ delivery.
My suspicion is that it's the IRQ itself that is the problem. Rather that it's something the core is doing in response to receiving it (for example, trying to fetch from the vector table).
Some questions: