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How to distribute single one SPI to multi PE concurrently in GIC-600 ?

duanlin

hello there,

I have a 1 cluster 4 cores SOC, the cores are all Cortex-A55. And a GIC-600 with it.
In my application, Run AMP applicaiton on it, 1 core for baremetal and other cores for linux.

There is one EINT on GPIO, which provides a precise signal of synchronization on whole board.
I wish the EINT can interrupt 2 AMP subsys concurrently.

I found that the IRQ affinity settings are like A.B.C.D in GIC-600, which have 4 dimensions and only one target finally. (Is it?)
in another working mode of GIC-600, it can automatically select one appropriate PE in the group for handling the IRQ. (Is it?)

I cannot find the way of distributing IRQ to multi PEs concurrently.

Thanks for your guide,
Lin.Duan

Jan 4, 2025

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  • +1 Arm Employee Badge

    For each SPI, GICv3 supports two targeting options:

    • Targeted - software specifies a target PE, the GIC will only deliver the interrupt to that PE.
    • 1ofN - each time the interrupt becomes Pending, the GIC will select a target PE and deliver it there - it might make a decision each time.
      • Note: Support for 1ofN is optional.

    In both models, a given instance of SPI interrupt can only be acknowledged on a single PE.  There's no mode in GICv3 to allow a single SPI to be delivered to and acknowledged by multiple PEs.

    If you need a peripheral interrupt to go to multiple PEs, the options are:

    • Target the SPI at one PE, have that PE send SGIs to the other PEs as part of its handler
    • Connect the interrupt source to multiple INTIDs (as in, wire the interrupt to multiple inputs on the GIC - so a design time decision)
Reply
  • +1 Arm Employee Badge

    For each SPI, GICv3 supports two targeting options:

    • Targeted - software specifies a target PE, the GIC will only deliver the interrupt to that PE.
    • 1ofN - each time the interrupt becomes Pending, the GIC will select a target PE and deliver it there - it might make a decision each time.
      • Note: Support for 1ofN is optional.

    In both models, a given instance of SPI interrupt can only be acknowledged on a single PE.  There's no mode in GICv3 to allow a single SPI to be delivered to and acknowledged by multiple PEs.

    If you need a peripheral interrupt to go to multiple PEs, the options are:

    • Target the SPI at one PE, have that PE send SGIs to the other PEs as part of its handler
    • Connect the interrupt source to multiple INTIDs (as in, wire the interrupt to multiple inputs on the GIC - so a design time decision)
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