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Cortex-R52+ asynchronous external abort

Grace WANG

Hi

The R52+ CPU goes to data abort and the DFSR is 0xA11 (asynchronous external abort for write access). I saw some tickets indicating that cache could lead to asynchronous abort.

I wonder whether the write-through cache can generate such asynchronous external abort ?

BR, Grace

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  • 0 Arm Employee Badge in reply to Grace WANG

    Cacheable accesses aren't the only place you'll get buffered writes, and buffered writes aren't the only possible cause of async external aborts.

    I'd approach it from a different angle - you know there is an external abort but not what is causing it.  So the question is: what could have caused it?  As in, given the memory system of your device, what are the potential things that would result in an external abort.  My suspicion is that you've not got the MPU set up correctly for the memory system of your device resulting in an access being generated that the memory system can't handle.  So if it was me, I'd be checking:

    • Do you have read-only memories that give bus-level faults on writes?  If yes, are those addresses mapped as read-only in the MPU?  
    • Do you have regions that give bus level faults on reads? If yes, are those regions marked as No Access/Not executable?  
    • Are all peripheral regions marked as Device and as not-executable?
    • Does the device support ECC and if so have you done any necessary initialisation?  
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  • 0 Arm Employee Badge in reply to Grace WANG

    Cacheable accesses aren't the only place you'll get buffered writes, and buffered writes aren't the only possible cause of async external aborts.

    I'd approach it from a different angle - you know there is an external abort but not what is causing it.  So the question is: what could have caused it?  As in, given the memory system of your device, what are the potential things that would result in an external abort.  My suspicion is that you've not got the MPU set up correctly for the memory system of your device resulting in an access being generated that the memory system can't handle.  So if it was me, I'd be checking:

    • Do you have read-only memories that give bus-level faults on writes?  If yes, are those addresses mapped as read-only in the MPU?  
    • Do you have regions that give bus level faults on reads? If yes, are those regions marked as No Access/Not executable?  
    • Are all peripheral regions marked as Device and as not-executable?
    • Does the device support ECC and if so have you done any necessary initialisation?  
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