Relation between Load/Store Physical Address (PA) and L1, L2, L3 Cache Set Number

In my understanding, the set number in a cache is obtained directly from the index bits in the Physical Address (PA). For example, for an L2 cache with a total of 4096 sets, we use the index bits PA[17:6] (12 bits in total) as the set number.

However, I found a statement in the X925 Technical Reference Manual (TRM) (https://developer.arm.com/documentation/102807/0001/L2-memory-system/L2-cache):

"The way that cache indices are determined means that there is no direct relationship between the Physical Address (PA) and set number. You cannot use targeted operations that assume a relationship between the PA and set number. To flush the entire cache, you must perform set and way maintenance operations over the number of sets and ways described in CCSIDR_EL1 for that cache. This operation is compliant with the Armv8-A architecture."

Could anyone please clarify this statement? Specifically, how are the cache indices determined if not directly from the PA ?

Thanks!