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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3624 Questions
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  • Not Answered

    How to Define msi_msg for Software-Generated Interrupts with GICv3 ITS? (linux kernel 6.12.y) 0

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    489 views
    1 reply
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Clock Gating Cell Missing Module 0

    • Clocking Structures & Timing Mechanisms
    785 views
    3 replies
    Latest 6 months ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    CMSDK Compile Error for Cortex-M0 0

    220 views
    0 replies
    Started 6 months ago
    by Alarik Unggul Yudhatama Sukadis
  • Suggested Answer

    order problem 0

    • AXI4
    970 views
    5 replies
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Interrupt table and handling in cortex-m0+ assembly 0

    • Cortex-M0+
    • Arm Assembly Language (ASM)
    507 views
    1 reply
    Latest 6 months ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    AArch64 - VMSAv8 - TLB - Where to store the ASID in block/page table entry 0

    • AArch64
    • Memory Management Unit (MMU)
    599 views
    1 reply
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Armv7-a TrustZone cps instruction Question 0

    1019 views
    5 replies
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Snoops for access to inner/outer shareable domain 0

    • corelink cmn-600
    • DSU
    566 views
    1 reply
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Two different OS on different cores in same cluster with no EL2 enabled 0

    • EL2
    920 views
    4 replies
    Latest 6 months ago
    by yifanfeng
  • Not Answered

    Why ARM A720AE treats non-shareable as non-cacheable? 0

    238 views
    0 replies
    Started 6 months ago
    by yifanfeng
  • Answered

    Cortex-M0 initialization | Minimum requirements 0

    • Cortex-M0
    721 views
    2 replies
    Latest 6 months ago
    by Igor
  • Suggested Answer

    Illegal Instruction Exception 0

    1268 views
    4 replies
    Latest 6 months ago
    by Peter Harris Arm Employee Badge
  • Not Answered

    SMP kernel over multi-cluster ARMv9 cores 0

    • GICv3/v4
    • DSU
    286 views
    0 replies
    Started 6 months ago
    by yifanfeng
  • Not Answered

    Inquiry: Does ARM Errata ID 838869 apply to Cortex-M7? +1

    • Cortex-M7
    1231 views
    1 reply
    Latest 7 months ago
    by Daniel Ka
  • Suggested Answer

    Cortex M3 sc300 DHCSR Regist 0

    802 views
    1 reply
    Latest 7 months ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    MPAM support in Linux mainline 0

    451 views
    0 replies
    Started 7 months ago
    by yifanfeng
  • Answered

    Unexpected result from svqdmulh_s32 with negative input values +2

    • intrinsics
    • NEON
    • Cortex-A
    • SVE2
    675 views
    1 reply
    Latest 7 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    SVE/SVE2 issue on Cortex-A320 example 0

    • SVE
    1450 views
    5 replies
    Latest 7 months ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Restrict Speculative Access +1

    984 views
    3 replies
    Latest 7 months ago
    by Youq
  • Answered

    In Cortex-R5, the address of cache maintenance operations is not restricted by the MPU ? 0

    • Cortex-R
    1156 views
    4 replies
    Latest 7 months ago
    by SmileSX
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