Cortex M3 sc300 DHCSR Regist

Hi there,

I'm trying to emulate the EDA to configure the DHCSR register of the SC300 through Jtag so that the SC300 can be halted.

I wrote the DHCSR register address 0xE000_EDF0 by configuring the AP's TAR register 0x4 and the AP's DRW register 0xC to write the value 0xA05F0003. But that didn't work. The SC300 does not respond to writing to the 0XC register.

I was wondering if I missed some other configuration before writing DHCSR. Or do you know the specific process of configuring the DHCSR register through JTAG? I need to emulate this process on the EDA.

Thank you so much!

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  • Here is the high-level flow for halting the SC300 through JTAG using the AHB-AP:

    Power up Debug via DPCTRL/STAT
    - Write 0x50000000 to 0x4 (DP_CTRL_STAT).
    - Poll for CDBGPWRUPACK | CSYSPWRUPACK in response.
    Select AHB-AP in DP SELECT
    - Write 0x00000000 to DP SELECT (0x8).

    Set TAR to DHCSR address

    Write 0xE000EDF0 to AP's TAR (0x4).

    Write unlock + halt command to DHCSR via DRW

    Write 0xA05F0003 to AP's DRW (0xC).

    Verify via read-back

    Read AP's DRW (0xC) and check that the S_HALT bit is set in DHCSR.

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  • Here is the high-level flow for halting the SC300 through JTAG using the AHB-AP:

    Power up Debug via DPCTRL/STAT
    - Write 0x50000000 to 0x4 (DP_CTRL_STAT).
    - Poll for CDBGPWRUPACK | CSYSPWRUPACK in response.
    Select AHB-AP in DP SELECT
    - Write 0x00000000 to DP SELECT (0x8).

    Set TAR to DHCSR address

    Write 0xE000EDF0 to AP's TAR (0x4).

    Write unlock + halt command to DHCSR via DRW

    Write 0xA05F0003 to AP's DRW (0xC).

    Verify via read-back

    Read AP's DRW (0xC) and check that the S_HALT bit is set in DHCSR.

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