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Hi All, I have two questions related to axi. In system, I have one master ,one interconnect and one slave.Q1: If master send write transaction to slave -> DMB-> send read transcation to slave, the order seem by slave should be same as older seem by master?Q2:How about If master don't use DMB, just wait bresp and then send read transcation. the order seem by slave is same as master? will it happen reorder case?Thanks a lot!
I think you're mixing up two things:
Issuing a barrier is software saying that it wants ordering for these accesses. It's up to the hardware to figure out how to achieve that (ideally efficiently). With AXI, it could achieve the specified ordering by sending the first access then waiting for the BRESP before sending the other. So your Q2 is how the hardware might deal with Q1.
Some other thoughts:
If you're working with a peripheral, typically I'd expect it to be mapped as Device with the nR (no re-order) attribute. In which case software wouldn't need to use a DMB to ensure those accesses arrived in order. See B2.10.2.2 Reordering in the rev L.b Arm Architecture Reference Manual for A-profile.
The way DMB is described is in terms of what another observer (e.g. a thread on another core) could observe, not in terms of what the end device. In your example, imagine that the slave is a memory and mapped as cacheable. In which case the writes might only make it as far as a cache, rather than the device. At some point the lines will be evicted from the cache, but there'd be no guarantee the lines would be evicted in the same order as they were filled. If what you care about is the order of arrival at the device, then it's Device type with nR that you'd typically use. Alternatively, software might use DSB - which has a different set of guarantees.
Thanks for reply.
But If the master write transaction to slave -> wait brsp and then send read transaction to slave. it can not ensure that the slave must receive the write transaction first and then read transaction? because interconnect may send brsp to master first, and the delay (from master write -> interconnect-> slave) may not same as (from master read -> interconnect-> slave) . In this case, the slave will receive read transaction and then write transaction, the order is not same as master's?