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What I'm trying to figure out is what the start and end modes are - can you confirm those from the CPSR?
The easiest explanation for r8-r12 appearing to change on a mode switch is that you have changed to or changed from FIQ mode - as FIQ mode has it's own banked copy of those registers. Therefore if you switch into or out of FIQ mode, it'll appear as if r8-r12 changed value because you're now seeing different values. So I'm interested in what mode the processor was in when the CPS instruction get executed and what mode the processor is in after the CPS when you look at the regs in the debugger.