Under Cortex-R5, the addresses for cache maintenance are not restricted by the MPU. For example, performing cache cleaning or invalidation operations on an address space without access permission will not cause any exceptions. For example, there are two contexts here called TaskA and TaskB, and during the task switching process, the OS is responsible for maintaining the memory permissions corresponding to each Task context; when TaskA is being executed on the CPU, if the CPU accesses the Memory Space of TaskB, it will be restricted by the MPU; however, at this time, it is allowed to perform a cache invalidation operation on address X belonging to TaskB while executing TaskA. Thus, if the address space corresponding to X is configured as Cacheable + write-back, incorrect cache maintenance behavior will cause Dirty Data in the cache to fail to be correctly written back to memory.