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AArch64 - VMSAv8 - TLB - Where to store the ASID in block/page table entry

Johannes Krottmayer

Hello community!

I have started a bare-metal kernel for the purpose of education. Currently trying to implement the user space (EL0). Have want to use the TLB maintenance operations which requires a valid ASID, to avoid invalidation from all tables. In the reference manual I have seen a specific ASID can be assigned to the addresses for the level 0 tables in TTBR0_EL1 or TTBR1_EL1, depending on the selected register in TCR_EL1 which hold the ASID.

Can this only be done in TTBR0_EL1 or TTBR1_EL1 and not in the table entries? Unfortunately I didn't find any hint in the reference manual. Neither in the upper nor in the lower attributes from the next level table or the block and page entries. If this can really only be done in the TTBRx_EL1 registers then I lack in the understanding for the purpose of the ASID.

Hope somebody can clarify that.

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  • +1 Arm Employee Badge
    Johannes Krottmayer said:
    Can this only be done in TTBR0_EL1 or TTBR1_EL1 and not in the table entries?

    Here's a summary of the controls:

    • TTBRx_EL1.ASID controls what the current ASID is.
    • TCR_EL1.A1 controls whether the ASID is specified in TTBR0_EL1 or TTBR1_EL1.
    • The nG field in the individual Page or Block mappings specify whether the entry is Global (applies to all ASIDs) or Non-Global (applies only the current ASID).

    Commonly, the top of the EL0/1 VA space (TTBR1)  is kernel space and the bottom (TTBR0) user space.  Which leads to the ASID being specified in TTBR0_EL1 (TCR_EL1.A1=0), with most of the entries in the TTBR0 tables being Non-Global and most of the entries in the TTBR1 tables being Global.  That's a simplification, and the details will vary from kernel to kernel.

    Note: FEAT_ASID2 (permitted from Armv9.4-A) changes things slightly, it enables you to use different ASIDs for TTBR0 vs TTRB1.

    There's a high-level overview here: https://developer.arm.com/documentation/101811/0104/Address-spaces/Address-Space-Identifiers---Tagging-translations-with-the-owning-process

    If the explanation doesn't help, or you think there are things missing, do let us know.  Feedback helps us improve the guides.

Reply
  • +1 Arm Employee Badge
    Johannes Krottmayer said:
    Can this only be done in TTBR0_EL1 or TTBR1_EL1 and not in the table entries?

    Here's a summary of the controls:

    • TTBRx_EL1.ASID controls what the current ASID is.
    • TCR_EL1.A1 controls whether the ASID is specified in TTBR0_EL1 or TTBR1_EL1.
    • The nG field in the individual Page or Block mappings specify whether the entry is Global (applies to all ASIDs) or Non-Global (applies only the current ASID).

    Commonly, the top of the EL0/1 VA space (TTBR1)  is kernel space and the bottom (TTBR0) user space.  Which leads to the ASID being specified in TTBR0_EL1 (TCR_EL1.A1=0), with most of the entries in the TTBR0 tables being Non-Global and most of the entries in the TTBR1 tables being Global.  That's a simplification, and the details will vary from kernel to kernel.

    Note: FEAT_ASID2 (permitted from Armv9.4-A) changes things slightly, it enables you to use different ASIDs for TTBR0 vs TTRB1.

    There's a high-level overview here: https://developer.arm.com/documentation/101811/0104/Address-spaces/Address-Space-Identifiers---Tagging-translations-with-the-owning-process

    If the explanation doesn't help, or you think there are things missing, do let us know.  Feedback helps us improve the guides.

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