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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3617 Questions
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  • Suggested Answer

    Difference between System mode, User mode and Supervisor mode in Cortex R. 0

    • Cortex R
    1710 views
    1 reply
    Latest 10 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Cortex-R5F core unexpected fetch reserve address 0

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    Latest 10 months ago
    by Martin Weidmann Arm Employee Badge
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    [ARM R52+] GIC distributor on R52+ with DCLS 0

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    Latest 10 months ago
    by steve jeong
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    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

    • ACE
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    1 reply
    Latest 10 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

    • Cortex-R5
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    Latest 10 months ago
    by ele
  • Not Answered

    Is there any way to use 2-DSU IPs in a same NI-Bus ? 0

    • DSU-120
    • DSU
    408 views
    0 replies
    Started 10 months ago
    by Sangu Park
  • Answered

    Secure Mode Switching in R5 0

    • cortexr5
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    1 reply
    Latest 10 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Request for Configuration and Usage Guide of PERIPH_PORT in Corinth 0

    • Cortex-A55
    • Cortex-A
    411 views
    0 replies
    Started 10 months ago
    by yiduan su
  • Answered

    What will happen when cacheline is mismatch 0

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    • Cortex-A
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    Latest 10 months ago
    by junhao.wang
  • Answered

    Does Cortex-A53 support Separate Start Address? 0

    • Cortex-A53
    1019 views
    1 reply
    Latest 11 months ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    582 views
    0 replies
    Started 11 months ago
    by Adithya SM
  • Suggested Answer

    Halt-on-debug scenario, halt the system counter when halting. 0

    • Cortex-A9
    • CoreSight Debug and Trace
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    2071 views
    5 replies
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

    1854 views
    5 replies
    Latest 11 months ago
    by Jake Zhao
  • Answered

    How to generate LPI with ITS? 0

    1062 views
    1 reply
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    870 views
    1 reply
    Latest 11 months ago
    by steve jeong
  • Answered

    Cortex-R52+ asynchronous abort 0

    • abort
    • Cortex-R52+
    1496 views
    3 replies
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

    • AMBA
    • AXI
    434 views
    0 replies
    Started 11 months ago
    by Manikanta Kopparapu
  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
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    • jetpack
    1952 views
    0 replies
    Started 11 months ago
    by Niklas Flink
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