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Hi all:
I have read some articles about exclusive instructions in ARM64. There is a simple soc logic diagram in one article, which is as follows.
multi-core processor is running linux and the other single processor is running rtos. Both linux and rtos have separate physical memory space.
It says that exclusive access to a spinlock(using ldxr, stxr) in linux just reqires the participation of local monitor and the cache coherency logic, but not the global monitor.
I doubt that since a spinlock variable in memory is shareable.
Can someone give me a hand to clarify it?
The Global Monitor is not necessarily a specific piece of hardware. Together, the Local Monitors and cache coherency logic can provide the function of a Global Monitor - namely:
A global monitor that marks a PA as exclusive access for a particular PE. This marking is used later to determine whether a Store-Exclusive to that address that has not been failed by the local monitor can occur. Any successful write to the marked block by any other observer in the shareability domain of the memory location is guaranteed to clear the marking.
FYI, there's currently no Learn the Architecture guide of atomics/exclusives, but one is planned.