Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Not Answered

    Debug Print Logs Display and Hardware Power Issue in KEIL uVision 5 (Cortex-M0) 0

    1252 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    SMMUv2 IRQS per Context Bank 0

    • SMMUv2
    744 views
    0 replies
    Started over 2 years ago
    by Jorge
  • Not Answered

    The pipeline of add with lsl >4 in Neoverse N1 0

    • Documentation
    • Neoverse N1
    875 views
    0 replies
    Started over 2 years ago
    by Juneyoung Lee
  • Not Answered

    Can I use a Single Linux OS to schedule two DSU cluster? 0

    • Embedded Linux
    • DynamIQ
    2203 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Enabling MPU causes clearing of Stack in Cortex R5F 0

    • Cortex-R5
    1297 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Tail Chaining 0

    • Interrupt Handling
    1143 views
    1 reply
    Latest over 2 years ago
    by Sue Wu Arm Employee Badge
  • Suggested Answer

    Is PendSV or counterpart available on Cortex-A? 0

    • Cortex-A
    • 14 (PendSV)
    1931 views
    2 replies
    Latest over 2 years ago
    by AndyBlue
  • Suggested Answer

    Cortex-A78 NEON instructions timing 0

    1780 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    How to obtain the AArch64 memory management examples mentioned in the document "Learn the architecture - AArch64 memory management examples" 0

    • AArch64
    • Memory Management Unit (MMU)
    • Memory Management
    3135 views
    4 replies
    Latest over 2 years ago
    by zhanlang
  • Answered

    Cortex-M4F: Assembly instruction SMLAxy (and some others) gives wrong result 0

    • Cortex-M4
    2636 views
    2 replies
    Latest over 2 years ago
    by Evgen Volkov
  • Suggested Answer

    What's the relationship between trace and SPE? 0

    • performance
    • arm streamline
    2000 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    ARMv8 trigger core dump 0

    1400 views
    2 replies
    Latest over 2 years ago
    by Pete_Gil
  • Not Answered

    A53: PMU - BUS_ACCESS_LD - Write-Streaming 0

    1188 views
    0 replies
    Started over 2 years ago
    by Chris_Ger
  • Not Answered

    CYCLONE V - HPS - DDR RAM CONTROL OVER JTAG WITH OPENOCD 0

    • Cortex-A9
    • JTAG
    • SoC FPGA
    • Baremetal
    1249 views
    0 replies
    Started over 2 years ago
    by ieeeHuseyin
  • Suggested Answer

    NIC400: What is the difference between ahblitetarget and ahbliteinitiator 0

    3151 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    ARMv8 Writing and reading to/from Debug Data Transfer Register 0

    3333 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [Cortex M0] tarmac on palladium emulator 0

    1035 views
    0 replies
    Started over 2 years ago
    by SujithCh8
  • Not Answered

    Cortex A9 L2 cache clean-invalidate timing issue 0

    • CoreLink L2C-310 Level 2 Cache Controller
    993 views
    0 replies
    Started over 2 years ago
    by hilchenbach
  • Not Answered

    NVIC and/or USART appears to hold pending requests stuck (Cortex-M0 in STM32L071) 0

    771 views
    0 replies
    Started over 2 years ago
    by AGrigoriev
  • Not Answered

    What improvements does FEAT_DoPD provide? 0

    • Architecture
    • External Hardware Debug
    819 views
    0 replies
    Started over 2 years ago
    by srLeslie
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone