Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Suggested Answer

    Socrates for SSE-315 subsystem 0

    1833 views
    2 replies
    Latest over 1 year ago
    by Ian J Arm Employee Badge
  • Suggested Answer

    gic-600 interconnection through AXI-Stream interface 0

    • gic
    1901 views
    2 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    What Causes Program Performance to Decline Despite an Increase in Cache Hit Rate? 0

    • Cortex-A76
    826 views
    0 replies
    Started over 1 year ago
    by y say
  • Not Answered

    ASIC AES in ARM CPU, on data bus 0

    • Security
    697 views
    0 replies
    Started over 1 year ago
    by Teddy Rahbe
  • Answered

    DVM operations in ARM ACE5 0

    4018 views
    7 replies
    Latest over 1 year ago
    by Rohith Jonnabhatla
  • Suggested Answer

    AXI Write Interleaving 0

    • AMBA
    • AXI3
    • AXI
    • AXI4
    2133 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Invisible system cache 0

    2512 views
    4 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Where I can get Implementation (iBEP) document for DSU 120 and Cortex-X925 +1

    1387 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    How to downlaod pdf of an online document 0

    • Cortex-M7
    • web
    • Documentation
    1243 views
    1 reply
    Latest over 1 year ago
    by frank_
  • Not Answered

    GPIO manipulation on A55 core of IMX93 with JTAG 0

    • JTAG
    • Cortex-A55
    • GPIO
    • uboot
    • secure
    1579 views
    0 replies
    Started over 1 year ago
    by Adam Honeybell
  • Not Answered

    Relationship between ARM's shareability domain, cache maintenance and barrier 0

    • Cache coherency
    • Armv8-A
    • barrier
    • memory-model
    • Cache Architecture
    • Memory Management
    2103 views
    2 replies
    Latest over 1 year ago
    by Joon Kang
  • Answered

    Return from MemManageFault +1

    • mpu
    • MemManageFault
    • Cortex-M4
    2247 views
    3 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Support for Huge Pages in SMMU 0

    • SMMUv3
    2816 views
    4 replies
    Latest over 1 year ago
    by Jonathan Kang
  • Answered

    Memory Frequencies per Core 0

    • Memory Management Unit (MMU)
    • Cortex-A
    • x1
    1751 views
    2 replies
    Latest over 1 year ago
    by FabianSchuetze
  • Answered

    Why might Loop Unrolling contribute to Lower Runtime When using two Cores (X1 or A76) but not with one Core? 0

    • Cortex-A76
    • Cortex-X
    1745 views
    2 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    ARM FM, CT M7 exception return, R7 register is not preserved 0

    795 views
    0 replies
    Started over 1 year ago
    by Torbjörn Andersson
  • Answered

    Cache impacted memory region when MPU disabled. 0

    • Cortex-M7
    • Cortex-M
    1400 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    What PMU Events describes Remote Reads 0

    • Performance Monitor Unit (PMU)
    1701 views
    2 replies
    Latest over 1 year ago
    by FabianSchuetze
  • Answered

    ARM V7 TZC to do access control DDR only 0

    • ddr
    • Armv7
    • cpu memory map
    • tzc-400
    1319 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    How is the "Bank" in A53's L2MERRSR defined in TRM? 0

    • a53
    663 views
    0 replies
    Started over 1 year ago
    by User_0182
<>