Hello,
I would like to confirm my understanding of the following transfer scenario:
What I Understand:
The slave requires the following information:
For a 4-byte data transfer, the lower 2 bits of the address are important. Therefore, "2'b01" is provided to the slave, and the valid data range is from 0x01 to 0x03, activating the corresponding strobe.
In summary, an unaligned transfer occurs only during the first transfer, while subsequent transfers are aligned.
Questions:
I would appreciate your clarification on this matter.
The reason the protocol needs a WRITE strobe signal is that the manager knows which byte lanes contain valid data, but the subordinate doesn't, so WSTRB gives the subordinate this information.
However for READ transactions, the manager already knows which byte lanes it actually wants data on, so the subordinate just needs to drive the ARSIZE requested amount of data, and the manager takes the actual byte lanes it is interested in (it can mask off the bytes it does not need).
The "unaligned" term in AXI is slightly misleading in that it only applies to the first transfers in an INCR transaction, so the AxADDR misalignment with the indicate AXSIZE transfer width tells you which byte lanes are not covered by the first "unaligned" transfer. All subsequent transfers in the INCR transaction are aligned to the AxSIZE value (for FIXED transaction types all transfers in the transaction keep the same unalignment).
For the address for multiple beats of an (initially) unaliged transfer, it would be the subordinate that needs to calculate each address in the transaction (AXI only ever sends the initial start address). So as covered above, only the first transfer in an INCR transaction is unaligned, and subsequent transfers are to aligned addresses, calculated by AxSIZE aligning the start address and then adding AxSIZE for each transfer.
So if you had an unaligned 4-transfer transaction to 0x1 with AxSIZE=0x2 (32-bit), the transfer addresses would be to 0x1, 0x4, 0x8 and 0xC.