AXI4 Unaligned transfer WRITEs and READs

I would like to understand the nature of unaligned transfers better in axi. The spec says

• Use the low-order address lines to signal an unaligned start address.
• Provide an aligned address and use the byte lane strobes to signal the unaligned start address.

How are these to be understood for WRITE and READ requests separately?


Consider an axi-manager issues a WRITE request for AWADDR = 0x09 AWLEN = 3 AWSIZE = 2 (32 bits) on a 32 bits of data channel.

1. How is WSTRB provided?
      a. Is it only 3 bits of WSTRB = 3'b111 on a 4 bit WSTRB lane? In such a case, should the WSTRB be assumed to be 4'b0111 and later appropriately handled inside the fabric implementation?
      b. Or does the manager send the appropriate WSTRB = 4'b1110 (which seems unlikely, as the manager is sending an unaligned address by a correct WSTRB)?

Moving to READ requests for the same unaligned transfers. ARADDR = 0x09, ARLEN = 3 ARSIZE=2 (32 bits) on a 32 bits of data channel.

1. How should this request be handled? Align the address to 0x08 and the manager should consider Upper 3 bytes of data only?

Can someone explain how both these requests are to be handled or managed as a HDL developer?

Your response is highly appreciated.



P.S.: AXI spec considered from IHI0022K issue.