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AXI4 unaligned transfer

DongGeon Lee

Hello,

I would like to confirm my understanding of the following transfer scenario:

  • Start Address: 0x01
  • Transfer Size: 32-bits
  • Burst Type: INCR
  • Burst Length: 4-beats

What I Understand:

The slave requires the following information:

  1. The lower bits of the start address.
  2. Byte lane strobe information.

For a 4-byte data transfer, the lower 2 bits of the address are important. Therefore, "2'b01" is provided to the slave, and the valid data range is from 0x01 to 0x03, activating the corresponding strobe.

In summary, an unaligned transfer occurs only during the first transfer, while subsequent transfers are aligned.

Questions:

  1. Is my understanding correct regarding how this transfer proceeds?
  2. If 32'hFFFF_FFFF is transmitted during the first transfer, how will the [31:24] bits be handled?

I would appreciate your clarification on this matter.

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