In the AXI4 protocol, write interleaving is no longer supported. Some argue that the effort and resources required to support write interleaving were too high, which led to its exclusion from the AXI4 protocol. However, when multiple masters with different transmission speeds attempt to perform write transactions simultaneously, the interconnect can become congested if write interleaving is not supported. This could decrease the throughput of the bus. So, what is the actual reason that write interleaving is not supported in the AXI4 protocol if there is potential performance degradation in some common scenarios? Are there any other pros and cons that need to be considered? And what exactly are the efforts and resources needed to support write interleaving?"
As an example for the extra complexity required by write data interleaving, consider routing multiple transactions of write data through an interconnect to different outputs.
If write data interleaving is supported, the routing block needs to maintain a look up structure of all the decoded AW requests that have not had their write data routed. To support many outstanding transactions (especially if same AWIDs are used) would require a complex structure.
By contrast, without write data interleaving, the routing block simply needs a FIFO storing the routing information as the all data is guaranteed to arrive in the same order as the requests.
Another example is for a subordinate receiving interleaved write data. The subordinate might perform most efficiently if it can write an entire request instead of individual write transfers. If the write data can arrive interleaved, the subordinate may need to be able to buffer many different transactions worth of write data to perform efficiently.
Without write data interleaving, the subordinate knows that it will receive all the write data for each request in the order that the requests arrive in.