ETE Instruction Trace Configuration

Hello,

I’m testing the CPU instruction trace feature in my SoC, and I’m following the ETM configuration example from section 4.5.1 in document ARM IHI0064H.b (ID101923). However, I never see ATVALID assert after all of the configuration has completed. 

Test sequence

1. Run program on CPU0 that prints a counter value in an infinite loop
2. Configure ETM and Debug registers according to the sequence in 4.5.1 through APB
3. Capture waveform
4. Observe that ATVALID never asserts 

Status registers checked

• TRCLSR.SLK [1] == 0 # software lock is cleared
• TRCLSR.SLI [0] == 1 # software lock implemented
• TRCOSLSR.OSLM {3, 0} == b10 # OS lock is implemented
• TRCOSLSR.OSLK [1] == 0 # OS lock is cleared
• TRCPDSR.OSLK [5] == 0 # OS lock is cleared
• TRCPDSR.STICKYPD [1] == 0 #  TRCOSLSR is valid and trace registers are valid
• TRCPDSR.POWER [0] == 1 # powered
• TRCSTATR.IDLE [0] == 0 # not idle
• EDSCR.TFO [31] == 1 # trace feature enable
• EDSCR.PIPEADV [25] == 1 # instruction execution is happening
• EDPRSR.OSLK [5] == 0 # OS lock is cleared

Are there any other status registers that I can check to ensure that my programming sequence is correct?