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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Not Answered

    Problems with the ATSAMD21G18-AU 0

    17418 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    AXI fixed burst to a slave with narrow data width 0

    • AXI
    • AXI4
    • Bus Architecture
    18291 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Regarding implementation of a scenario in AHB protocol 0

    17275 views
    4 replies
    Latest over 6 years ago
    by Suyash Sharma
  • Suggested Answer

    How could CMN600 route snoop transactions to RN-F 0

    16135 views
    2 replies
    Latest over 6 years ago
    by Joe Chen
  • Answered

    Application scenarios of APB4 0

    15899 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Outstanding support in AXI slave 0

    20389 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Question about AXI Exclusive Access Process 0

    21443 views
    6 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 ordering 0

    22194 views
    6 replies
    Latest over 6 years ago
    by Hyunkyu
  • Suggested Answer

    Where to find CHI protocol checkers and CHI testbench ? 0

    • AMBA
    • CHI
    22365 views
    6 replies
    Latest over 6 years ago
    by Jeremy_PENG
  • Answered

    AHB Bus Protocol -- Address Phase +1

    • Address
    • AHB-Lite
    29913 views
    9 replies
    Latest over 6 years ago
    by eugch
  • Not Answered

    Can I use AXI speck for Udemy classes 0

    18074 views
    4 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Exception handlers and interrupt 0

    • CoreLink GIC-400
    • Cortex-A53
    • Corelink
    • Cortex-A5
    • Generic Interrupt Controller
    • Cortex-A
    • Interrupt
    19963 views
    3 replies
    Latest over 6 years ago
    by c0deface
  • Not Answered

    Instruction and data cache dump from a-53 0

    14101 views
    0 replies
    Started over 6 years ago
    by RCReddy
  • Not Answered

    Why do LPIs in GIC have no "active" state? 0

    15169 views
    1 reply
    Latest over 6 years ago
    by Joe Chen
  • Suggested Answer

    outstanding transaction in AXI4 protocol 0

    15917 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Aligned and unaligned word transfers on a 64-bit bus +1

    • AXI
    • AXI4
    28247 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Lock Signal for AXI Slave +1

    • AXI
    17771 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Request for advise on better ARM learning path for VLSI engineer 0

    • FPGA
    16498 views
    2 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Fast model : Is there any way to overwrite PVBUS master id without using components which have id parameter (e.g. master_id, cluster_id ) 0

    • Fast Models
    15242 views
    1 reply
    Latest over 6 years ago
    by Jon Black Arm Employee Badge
  • Suggested Answer

    The meanings of AxCACHE 0

    19642 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
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Topics being discussed in this forum
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