AXI3 WRAP burst

I'm not sure if you are asking why WRAP burst transfers need to use AxSIZE aligned addresses, or why you might use a WRAP burst that doesn't actually wrap because it starts at the wrap boundary.

So to answer the first case, you need to use an AxSIZE aligned start address so that you can easily calculate the wrap boundary, and can perform all the data transfers required in the 2, 4, 8 or 16 transfers signalled by AxLEN.

And for the latter scenario, you might have a master designed to always use WRAP burst types because it always performs cache line type accesses, wanting to fetch in the critical data first and then complete the cache line entries after the critical data. But if the critical data IS the first entry on the cache line, the WRAP burst wouldn't then need to wrap. It would be adding more complexity to detect this one scenario and use an INCR type burst, so simply using WRAP accesses for all cache access is a simpler design.  

I'm not sure if you are asking why WRAP burst transfers need to use AxSIZE aligned addresses, or why you might use a WRAP burst that doesn't actually wrap because it starts at the wrap boundary.

So to answer the first case, you need to use an AxSIZE aligned start address so that you can easily calculate the wrap boundary, and can perform all the data transfers required in the 2, 4, 8 or 16 transfers signalled by AxLEN.

And for the latter scenario, you might have a master designed to always use WRAP burst types because it always performs cache line type accesses, wanting to fetch in the critical data first and then complete the cache line entries after the critical data. But if the critical data IS the first entry on the cache line, the WRAP burst wouldn't then need to wrap. It would be adding more complexity to detect this one scenario and use an INCR type burst, so simply using WRAP accesses for all cache access is a simpler design.