I'm working with the Cortex-M on digilent ARTY FPGA platform. I'm wondering how handling invalid address requests happen on a typical system. I'm guessing the address decoder in the AXI crossbar interconnect handles it somehow. Does it return an error condition to the master which raises a busfault? Or does it raise a busfault directly?
There must be a standard way of handling this as any SoC integration handles busfaults resulting from invalid memory accesses. Any guidance would be appreciated.
The AXI crossbar will have address decoders to work out which slave to pass a transaction to, and if the supplied address does not map to any assigned slave address range the crossbar will probably* return a DECERR response, and then it is up to the AXI master how it uses that error notification.
*I said "probably" because that's how the ARM AXI crossbars work, but in theory you could instead have a crossbar that uses other ways of indicating a busfault, for example using an interrupt. But I haven't seen this done.
It is also theoretically possible that the crossbar might not return any DECERR responses if the system or area being addressed needs to implement some sort of "secure" function. By returning error responses to addresses not implemented might give a hacker some idea of what they are trying to attack.