I'm working with the Cortex-M on digilent ARTY FPGA platform. I'm wondering how handling invalid address requests happen on a typical system. I'm guessing the address decoder in the AXI crossbar interconnect handles it somehow. Does it return an error condition to the master which raises a busfault? Or does it raise a busfault directly?
There must be a standard way of handling this as any SoC integration handles busfaults resulting from invalid memory accesses. Any guidance would be appreciated.