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Hi ARM experts,
I am configuring a network in which data width of busmatrix is 32bit and data with of slave is 64bit.
In write transaction, high half and low half of wstrb_slave[7:0] toggles interleavly, and it is quiet reasonable.
However, in read transaction, it seems that pl301 just bypasses the transaction from slave to master.
In my opinion, the duration of rvalid to master should be twice of the duration from slave.
How can I fix this problem?