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Programming the ARM NIC-301 QoS

Dakshina

I am currently working with the S32V234 board which features a ARM-NIC 301 Quality of Service Module

I have referred to the "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0451b/DDI0451B_corelink_qos301_advanced_quality_of_service_r0p1_trm.pdf" manual for the same.

I have some questions regarding the same 

  1. How can I find the base address of the NIC-301 device. The manual mentions that there are memory mapped registers like the qos_cntl registers which are at an offset from the "base address". The Global Programmer's view (and the memory map provided) was not clear. 
  2. Is it possible to program the registers at EL0. Or should we change the exception level. 
  3. Can the configuration settings be done at run time via a kernel module or is it necessary to change the settings at the bootcode itself.
  4. Is it possible to set the outstanding transaction limit per core or does the interconnect view the entire cluster as one unit.
  5. Is there an example code snippet to configure these registers programmatically. I dont have access to the AMBA designer. 
Parents
  • +1
    Dakshina said:
    How can I find the base address of the NIC-301 device. The manual mentions that there are memory mapped registers like the qos_cntl registers which are at an offset from the "base address". The Global Programmer's view (and the memory map provided) was not clear. 

    This would be specific to the S32V234 configuration of the NIC-301.  Hopefully it's in the documentation somewhere.

    Dakshina said:
    • Is it possible to program the registers at EL0. Or should we change the exception level. 

    You likely need to be in a secure state in order to program the NIC-301.  EL0 and EL1 can be either secure or non-secure.  EL3 will always be secure.

    Dakshina said:
    Can the configuration settings be done at run time via a kernel module or is it necessary to change the settings at the bootcode itself.

    Afraid that's outside my knowledge.

    Dakshina said:
    • Is it possible to set the outstanding transaction limit per core or does the interconnect view the entire cluster as one unit.

    The interconnect will see the cluster as a whole, as the interconnect is thinking in terms of interfaces.

    Dakshina said:
    there an example code snippet to configure these registers programmatically. I dont have access to the AMBA designer. 

    I'm not aware of any example code for this.  It's possible there's driver code available somewhere.

Reply
  • +1
    Dakshina said:
    How can I find the base address of the NIC-301 device. The manual mentions that there are memory mapped registers like the qos_cntl registers which are at an offset from the "base address". The Global Programmer's view (and the memory map provided) was not clear. 

    This would be specific to the S32V234 configuration of the NIC-301.  Hopefully it's in the documentation somewhere.

    Dakshina said:
    • Is it possible to program the registers at EL0. Or should we change the exception level. 

    You likely need to be in a secure state in order to program the NIC-301.  EL0 and EL1 can be either secure or non-secure.  EL3 will always be secure.

    Dakshina said:
    Can the configuration settings be done at run time via a kernel module or is it necessary to change the settings at the bootcode itself.

    Afraid that's outside my knowledge.

    Dakshina said:
    • Is it possible to set the outstanding transaction limit per core or does the interconnect view the entire cluster as one unit.

    The interconnect will see the cluster as a whole, as the interconnect is thinking in terms of interfaces.

    Dakshina said:
    there an example code snippet to configure these registers programmatically. I dont have access to the AMBA designer. 

    I'm not aware of any example code for this.  It's possible there's driver code available somewhere.

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