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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 739 Questions
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  • Not Answered

    How do I use M1 designstart fpga on Nexys4 DDR? 0

    11362 views
    0 replies
    Started over 6 years ago
    by Roy Kravitz
  • Not Answered

    Question related to Phases in APB 0

    18379 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Is M3 DesignStart similar to M7 Design Kit? (I don't yet have M7 Design Kit) 0

    • Cortex-M7
    • Cortex-M3
    • DesignStart
    12643 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    How to process raw data from monitor and convert it into set of commands + data exchange? 0

    11575 views
    0 replies
    Started over 6 years ago
    by aditya raja
  • Not Answered

    ARM-A15 SoC integration for Simulation (VCS) How to Enable traces for debug 0

    12102 views
    0 replies
    Started over 6 years ago
    by Moti88
  • Answered

    I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0

    14977 views
    1 reply
    Latest over 6 years ago
    by aditya raja
  • Not Answered

    Coresight Architecture: Is it possible to include AHB ROM tables as part of system ROM table? 0

    • CoreSight Architecture
    • CoreSight
    12768 views
    0 replies
    Started over 6 years ago
    by Vignesh J
  • Not Answered

    Executable name in DS-5 Linux project 0

    • DS-5 Development Studio
    • executable
    • compilation
    • Linux
    12340 views
    0 replies
    Started over 6 years ago
    by Yakov Erlich
  • Not Answered

    AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0

    18221 views
    1 reply
    Latest over 6 years ago
    by guimers8
  • Not Answered

    Missing CoreSight components in /renensas/r8a77970.dtsi 0

    • CoreSight Trace Funnel
    • replicator
    • TPIU
    • AMBA 3 ATB Interface
    • CoreSight System Trace Macrocell (STM)
    13066 views
    0 replies
    Started over 6 years ago
    by LWT
  • Not Answered

    simple design verilog code 0

    13102 views
    0 replies
    Started over 6 years ago
    by legend137
  • Answered

    WSTRB calculation 0

    16787 views
    2 replies
    Latest over 6 years ago
    by Ravi V.
  • Answered

    Handshaking for the write data channel 0

    16174 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Looking for manufacturer to produce our motherboard design 0

    14994 views
    0 replies
    Started over 6 years ago
    by Fran Saez
  • Not Answered

    AXI3 locked access +1

    • AMBA
    • AXI
    18544 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    WID not present in AXI4 0

    16551 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0

    13621 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Handling invalid AXI address requests 0

    • AXI4-Lite
    • Cortex-M System Design Kit
    • Cortex-M
    16927 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI INC type transfer 0

    14550 views
    2 replies
    Latest over 6 years ago
    by Ravi V.
  • Answered

    Question about AXI4 WLAST 0

    16851 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
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