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WID not present in AXI4

Ravi V.

can you clarify to me, why there is no WID in AXI4?

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  • +1

    WID is needed to support write data interleaving described in AXI3, but this isn't supported in AXI4, so no requirement to have a WID signal.

    See section A5.4.1 in the current AXI protocol spec for details of this.

    And as section A5.4.2 states, if you have an AXI3 legacy deisgn which needs a WID input, this can be generated using the ID conveyed on AWID.

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  • +1

    WID is needed to support write data interleaving described in AXI3, but this isn't supported in AXI4, so no requirement to have a WID signal.

    See section A5.4.1 in the current AXI protocol spec for details of this.

    And as section A5.4.2 states, if you have an AXI3 legacy deisgn which needs a WID input, this can be generated using the ID conveyed on AWID.

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