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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    ARMv9 core (such as A720)can bring VMID(or StreamID) to external fabric? 0

    • virtualization
    • Armv9
    549 views
    1 reply
    Latest 3 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    GIC-600 How to drop down ICC_RPR_EL1 to normal 0xFF without INTID 0

    687 views
    2 replies
    Latest 3 months ago
    by duanlin
  • Answered

    ARM®︎ Cortex®︎-A53 MPCore Processor rev. r0p4 lint errors +1

    • Cortex-A53
    • lint
    • asic
    524 views
    1 reply
    Latest 3 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    machine code opcodes 0

    500 views
    1 reply
    Latest 4 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Question about AMBA CHI_C2C spec.A credit 0

    528 views
    1 reply
    Latest 4 months ago
    by Simone Secchi Arm Employee Badge
  • Not Answered

    snooping transactions or non-snooping transactions for non-cacheable access? 0

    • Cache coherency
    • snoop
    • ACE
    • Armv8-A
    • coherency
    273 views
    0 replies
    Started 4 months ago
    by Lei Xu
  • Answered

    Question about CHI spec +1

    • CHI
    • C2C
    1224 views
    5 replies
    Latest 4 months ago
    by Ben Hicks Arm Employee Badge
  • Suggested Answer

    What is considered "good" and "average" pipeline utilization? 0

    • DSP
    • Pipeline Control and Execution
    • performance analysis
    • Cortex-M4
    634 views
    1 reply
    Latest 4 months ago
    by vstehle Arm Employee Badge
  • Answered

    about global monitor 0

    • global monitor
    • Armv8-A
    612 views
    1 reply
    Latest 4 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    How to know the interrupt ID which is signaled currently without acknowledging it 0

    • Interrupt Handling
    • EL2
    • AArch64
    • GICv3/v4
    • Hypervisor
    657 views
    1 reply
    Latest 4 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How do I get a FVP_BaseR_Cortex-R52x2? 0

    • Cortex-R
    967 views
    3 replies
    Latest 4 months ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Hardware implementation of vector load/store instructions on the CM55 core 0

    • Cortex-M55
    • optimization
    • Cortex-M
    • Vectorization
    395 views
    0 replies
    Started 4 months ago
    by Oleksandr Tymoshenko
  • Not Answered

    Disable HW Prefetcher On Pixel 8 0

    • EL1
    • Android
    • EL2
    • AArch64
    • pixel8
    • Arm9
    • HWprefetcher
    • Linux
    498 views
    0 replies
    Started 4 months ago
    by Gal Kaptsenel
  • Answered

    Will these two different data storage methods and MPU settings affect CPU efficiency? 0

    • mmu
    • mpu
    • Cortex-A
    • Cortex-M
    666 views
    1 reply
    Latest 5 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    APB: Support Write Enable mask? 0

    • APB
    • Architecture
    • Memory
    730 views
    1 reply
    Latest 5 months ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Is using WFI with PIT-based scheduler safe in bare-metal on S32K311? 0

    • timer
    • wfi
    369 views
    0 replies
    Started 5 months ago
    by nowkoes
  • Not Answered

    ARM Cortex-M3 Priority 0

    443 views
    0 replies
    Started 5 months ago
    by vignesh varadaraj
  • Not Answered

    A53 core not going into WFI sometimes. 0

    832 views
    2 replies
    Latest 5 months ago
    by Diptendu
  • Suggested Answer

    Clarification on Instruction Cache Availability in Cortex-M33 IP 0

    903 views
    1 reply
    Latest 5 months ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    How to know the APSEL number when there are multiple APs? 0

    • adi
    336 views
    0 replies
    Started 5 months ago
    by si huibin
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