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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3611 Questions
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  • Not Answered

    Inquiry: Does ARM Errata ID 838869 apply to Cortex-M7? +1

    • Cortex-M7
    1126 views
    1 reply
    Latest 5 months ago
    by Daniel Ka
  • Suggested Answer

    Cortex M3 sc300 DHCSR Regist 0

    737 views
    1 reply
    Latest 5 months ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    MPAM support in Linux mainline 0

    368 views
    0 replies
    Started 5 months ago
    by yifanfeng
  • Answered

    Unexpected result from svqdmulh_s32 with negative input values +2

    • intrinsics
    • NEON
    • Cortex-A
    • SVE2
    631 views
    1 reply
    Latest 5 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    SVE/SVE2 issue on Cortex-A320 example 0

    • SVE
    1343 views
    5 replies
    Latest 5 months ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Restrict Speculative Access +1

    908 views
    3 replies
    Latest 6 months ago
    by Youq
  • Answered

    In Cortex-R5, the address of cache maintenance operations is not restricted by the MPU ? 0

    • Cortex-R
    1070 views
    4 replies
    Latest 6 months ago
    by SmileSX
  • Not Answered

    Configure MPAM in Hypervisor even if virtual machine OS did not take care of MPAMx_EL1 0

    264 views
    0 replies
    Started 6 months ago
    by yifanfeng
  • Not Answered

    The CM7 CoreMark score is not ideal. 0

    272 views
    0 replies
    Started 6 months ago
    by depei zhang
  • Not Answered

    ACE - CHI protocol conversion 0

    272 views
    0 replies
    Started 6 months ago
    by Arjun Singh
  • Not Answered

    Use of smlad in arm_fir_decimate_fast_q15 function 0

    270 views
    0 replies
    Started 6 months ago
    by John Atkins
  • Answered

    Direct injection of SPIs 0

    • GICv3/v4
    • GIC Hypervisor Direct Injection
    1138 views
    4 replies
    Latest 6 months ago
    by yifanfeng
  • Answered

    In CHI WriteNoSnp transaction, why DBID is required in COMP response from completer? 0

    • CHI
    682 views
    1 reply
    Latest 6 months ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Can I (and how to properly) share DTCM with DMA in Cortex-M7 0

    • Cortex-M7
    452 views
    0 replies
    Started 6 months ago
    by Yujian Zhang
  • Not Answered

    ARM Cortex R52+ Data Cache Misses mis-calculation 0

    • Cortex-R52
    • Cache
    • Cache Architecture
    343 views
    0 replies
    Started 6 months ago
    by Alessandro Comodi
  • Answered

    C2C Snoop address mapping between CHI 0

    • snoop
    • CHI
    • C2C
    602 views
    1 reply
    Latest 6 months ago
    by Ben Hicks Arm Employee Badge
  • Answered

    C2C SNP Address width diff from CHI 0

    • CHI
    • C2C
    1887 views
    7 replies
    Latest 6 months ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Question about the performance overhead introduced by the MTE mechanism 0

    • performance
    • Cortex-A
    • MTE
    • SPEC2017
    739 views
    0 replies
    Started 6 months ago
    by Peng Mingfan
  • Not Answered

    Where can I find the description of hwcpipe_counter? 0

    303 views
    0 replies
    Started 6 months ago
    by Qing Chen
  • Not Answered

    ARMv8 halt address after reset with EDECR.RC set 0

    • Armv8-R
    339 views
    0 replies
    Started 6 months ago
    by Lee Leon
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