clarifications about ARCACHE bits in AXI4

the definition  of ARCACHE[3] is mentioned below. and also it is used in identifying the write back and write through memory type encoding in AXI4. 

as this bit is used in memory type encoding , in which cases the below definition will be used. why there are two definitions for the same signal ?

ARCACHE[3] Other Allocate When asserted, the transaction must be looked up in a cache because it could have been allocated in the cache by another transaction, either a write transaction or a transaction from another master. The transaction must also be looked up in a cache if ARCACHE[2] is asserted. When deasserted, if ARCACHE[2] is also deasserted, then the transaction does not need to be looked up in a cache.

could you please clarify ?

Parents
  • Table A4-5 Memory type encoding

    ARCACHE[3:0] AWCACHE[3:0] Memory type

    0000                    0000           Device Non-bufferable

    0001                    0001           Device Bufferable

    0010                     0010         Normal Non-cacheable Non-bufferable

    0011                     0011          Normal Non-cacheable Bufferable

    above table has definition for memory types

    Table A4-4 ARCACHE bit allocations


    ARCACHE[1] Modifiable When asserted, the characteristics of the transaction can be modified and a larger quantity of read data can be fetched than is required. When deasserted the characteristics of the transaction must not be modified.

    Thanks for providing clarifications. why there are two definitions mentioned for same signals .in which contexts these are used

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  • Table A4-5 Memory type encoding

    ARCACHE[3:0] AWCACHE[3:0] Memory type

    0000                    0000           Device Non-bufferable

    0001                    0001           Device Bufferable

    0010                     0010         Normal Non-cacheable Non-bufferable

    0011                     0011          Normal Non-cacheable Bufferable

    above table has definition for memory types

    Table A4-4 ARCACHE bit allocations


    ARCACHE[1] Modifiable When asserted, the characteristics of the transaction can be modified and a larger quantity of read data can be fetched than is required. When deasserted the characteristics of the transaction must not be modified.

    Thanks for providing clarifications. why there are two definitions mentioned for same signals .in which contexts these are used

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