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Setting up cache coherent transactions using CCI-500

Salkin

Background:

We have got a cache coherent network which includes an ACE-lite master (A simple datamover), an ACE master (Cluster with two Cortex-A72 sharing a level 2 cache) and the CCI-500 which is used as an interconnect. In our setup we are sending data via the datamover to the main memory which is used by the Cortex-A72 cluster. To implement cache coherent transactions we have done the following

  • Set the awcache signal to 0xF to use a "write-back with allocate" policy
  • Enabling the CCI-500 to send snoops to the ACE-master (CCI-500 Cache Coherent Interconnect, pp. 30).

Question:

Why do we need the ACE slave interface in the CCI-500 to enable snoops to the ACE master by writing to the appropriate register? Since the "AMBA AXI and ACE Protocol Specification" states that a "WriteBack" transaction does not cause a snoop of any masters, I would have assumed, that we do not need to enable snoops. 

  • 0 Arm Employee Badge

    WriteBacks are one kind of transaction related to coherency, but is not the primary transaction type that relates to your query.

    Your ACE-Lite manager is expected to issue ReadOnce and WriteUnique / WriteLineUnique transactions to be coherent with the CPU cluster.  These will check the CPU Cluster cache via snoops if it is possible that the CPU has cached the requested cache line.

    Snoops need to be explicitly enabled as otherwise there is a risk that a snoop request will be sent to the CPU Cluster when it is not able to respond to the snoop.  If this happens, the system will crash as the snoop must be completed in order to complete the request.