Setting up cache coherent transactions using CCI-500

Background:

We have got a cache coherent network which includes an ACE-lite master (A simple datamover), an ACE master (Cluster with two Cortex-A72 sharing a level 2 cache) and the CCI-500 which is used as an interconnect. In our setup we are sending data via the datamover to the main memory which is used by the Cortex-A72 cluster. To implement cache coherent transactions we have done the following

• Set the awcache signal to 0xF to use a "write-back with allocate" policy
• Enabling the CCI-500 to send snoops to the ACE-master (CCI-500 Cache Coherent Interconnect, pp. 30).

Question:

Why do we need the ACE slave interface in the CCI-500 to enable snoops to the ACE master by writing to the appropriate register? Since the "AMBA AXI and ACE Protocol Specification" states that a "WriteBack" transaction does not cause a snoop of any masters, I would have assumed, that we do not need to enable snoops.