I'm using an LPC1114 with cortex-m0 core with a keypad. I set up 4 column pins as input with pullups and 4 row pins as output with LOW level. So I'm detecting a LOW level on column pins, which are all on one port.
Based on my debug results, I occasionally detect the MIS register to be all zero, instead of having a 1 for the column that has a depressed button. Based on the spec sheet and google AI, this seems to be happening because MIS will reset if the active level is no longer present between when the CPU detects the interrupt and when the ISR reads MIS.So I wonder how many CPU cycles are needed to detect a GPIO level interrupt. The language below is a bit ambiguous and may only apply to edge interrupt, unless it applies to both? Thanks!
https://developer.arm.com/documentation/dui0497/a/cortex-m0-peripherals/nested-vectored-interrupt-controller/level-sensitive-and-pulse-interrupts