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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    how to set endianness in ARM Cortex-A8 +1

    • DS-5 Development Studio
    • Cortex-A
    • Cortex-A8
    29887 views
    15 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    What does an AHB slave do after issuing an ERROR, if the master decides to carry out the remaining transfers of the burst? +2

    • AMBA
    • AHB
    4553 views
    1 reply
    Latest over 10 years ago
    by Xiaotao Wang
  • Answered

    Support for pipelining flops in AXI +1

    • AXI
    • AXI4
    13089 views
    5 replies
    Latest over 10 years ago
    by Xingguang Feng Arm Employee Badge
  • Answered

    About AXI4 address channel and data channel handshake sequence +1

    • AMBA
    • AXI
    • AXI4
    7339 views
    1 reply
    Latest over 10 years ago
    by Xiaotao Wang
  • Answered

    AMBA AXI :Unaligned "INCR" data transfer +1

    • AMBA
    • AXI
    7594 views
    2 replies
    Latest over 10 years ago
    by Xiaotao Wang
  • Answered

    How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size? +1

    • AMBA
    • AXI
    • ACE-Lite
    • Cortex-A
    • Cortex-A7
    4393 views
    1 reply
    Latest over 10 years ago
    by Xingguang Feng Arm Employee Badge
  • Not Answered

    Indication to begin a program 0

    • Cortex-M0
    • 32-bit
    • Armv7-M
    • Cortex-M
    • 64-bit
    • Cortex-M4
    5867 views
    8 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    updating CPSR in USER UNPRIVILEGED mode 0

    • Armv7-A
    • Cortex-A
    • Cortex-M
    • Cortex-M4
    13632 views
    10 replies
    Latest over 10 years ago
    by Gopal Amlekar
  • Not Answered

    Can we run the Cortex-A53 cores at different clock speeds ? 0

    • Cortex-A53
    • Cache
    • Cortex-A
    9587 views
    5 replies
    Latest over 10 years ago
    by Ravinder
  • Not Answered

    ARM Cortex-R5 based Lock-step feature demonstration real time application? 0

    • Cortex-R
    • Cortex-R5
    8777 views
    5 replies
    Latest over 10 years ago
    by Ravinder
  • Not Answered

    I am currently an eighth grader but I have a deep interest in ARM processors, since I'm a neophyte but I have great interest could u tell me what makes ARM processors so significant? Why? Thank you :) 0

    • Armv7-A
    • Armv7-R
    • Cortex-M
    • C
    8885 views
    8 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    Supported AXI transfers on Cortex-A9? +1

    • 32-bit
    • Cortex-A9
    • AXI4
    • Cortex-A
    • 64-bit
    11997 views
    9 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    On Chip RAM is slow after enabling MMU, and using external ram aborts +1

    • Cache
    • Cortex-A
    • Cortex-A8
    7166 views
    4 replies
    Latest over 10 years ago
    by Gopu
  • Answered

    [CM3]UART always lose the last char 0

    • uart
    • Cortex-M3
    • Cortex-M
    6679 views
    6 replies
    Latest over 10 years ago
    by stupidMokey
  • Answered

    Which ARM processor is HSA compatible? +1

    • big.LITTLE
    • Cortex-A
    5471 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    Please let me know about different between "block entry" and "table entry" in VMSAv8-64 Translation table 0

    • Armv8
    9558 views
    2 replies
    Latest over 10 years ago
    by Jongseok Kim
  • Answered

    ARM1136: why the mismatch between cache stalls and cache misses ?? +1

    • Processor
    • Cache
    • Arm11
    11151 views
    10 replies
    Latest over 10 years ago
    by Zhan Chen
  • Answered

    Question about application of PendSV 0

    • Cortex-M
    • Cortex-M4
    26441 views
    8 replies
    Latest over 10 years ago
    by Gopal Amlekar
  • Answered

    Cache Memory Requirement 0

    • Cortex-R
    • Cache
    • Cortex-A
    • Cortex-M
    9131 views
    6 replies
    Latest over 10 years ago
    by Jerome Decamps - 杜尚杰
  • Answered

    ARM Cortex M3 STM32F207 processor hangs during the initializing if the code-size is more then 64k 0

    • Cortex-M3
    • Cortex-M
    4743 views
    2 replies
    Latest over 10 years ago
    by Stefan Tesche
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Topics being discussed in this forum
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  • AMBA
  • Arm Assembly Language (ASM)
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