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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    If CAN receive buffer is'nt cleared before a new message arrives,will it over-write the earlier data? 0

    • Cortex-M3
    • Cortex-M
    7311 views
    3 replies
    Latest over 10 years ago
    by Allen Willson
  • Answered

    Cortex-A9 core registers 0

    • Cortex-A9
    • Cortex-A
    6961 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    Can AXI data channel drop a burst? 0

    • AXI
    3360 views
    1 reply
    Latest over 10 years ago
    by Xingguang Feng Arm Employee Badge
  • Answered

    ARMv8 Secure EL1 problem 0

    • EL1
    • Armv7-A
    • Armv8-A
    • AArch32
    14456 views
    8 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to do cache invalid on Cortex-A53? +1

    • Cortex-A53
    • Cache
    • Cortex-A
    11477 views
    5 replies
    Latest over 10 years ago
    by yan.wy
  • Answered

    AXI4: Write-Alignemnent modes? Partial writing with write strobes possible? 0

    • 32-bit
    • AXI
    • AXI4
    17408 views
    8 replies
    Latest over 10 years ago
    by David Harriman-Smith Arm Employee Badge
  • Not Answered

    The new high performance ARM Cortex M7 Introduction 0

    • Cortex-M7
    • Cortex-M
    5367 views
    5 replies
    Latest over 10 years ago
    by Alban Rampon
  • Answered

    bootloader writing +2

    • Cortex-A
    • Cortex-A8
    • Cortex-M
    17636 views
    7 replies
    Latest over 10 years ago
    by Jerome Decamps - 杜尚杰
  • Answered

    hi. i wonder Register Slice of AMBA 3.0 AXI 0

    • AMBA
    • AXI
    12391 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Need help to decide on which ARM board to go for? 0

    • Cortex-M0
    • Cortex-M
    20362 views
    21 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    A strange problem in porting secure os in v8 secure EL1 0

    • 32-bit
    • AArch64
    • Armv8-A
    7368 views
    4 replies
    Latest over 10 years ago
    by Steven Meng
  • Answered

    which processors are very advanced processors +1

    • Cortex-A72
    • Cortex-R
    • Cortex-A17
    • Cortex-A15
    • Cortex-A
    • 64-bit
    • Cortex-R7
    6598 views
    3 replies
    Latest over 10 years ago
    by Alban Rampon
  • Answered

    Cortex-A7 initialization code & TrustZone/ Secure Boot 0

    • Raspberry Pi
    • Cortex-A
    • Cortex-A7
    • TrustZone
    16657 views
    5 replies
    Latest over 10 years ago
    by Vincent Siles
  • Answered

    hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving 0

    • AMBA
    • AMBA 3
    • AXI3
    • AXI
    10693 views
    2 replies
    Latest over 10 years ago
    by In-Gyu.Lee
  • Answered

    hi. i wonder AMBA 3.0 AXI out-of order - WID & RID 0

    • AMBA
    • AMBA 3
    • AXI
    29634 views
    10 replies
    Latest over 10 years ago
    by In-Gyu.Lee
  • Answered

    serial wire debug +1

    • Cortex-M
    • Cortex-M4
    2911 views
    1 reply
    Latest over 10 years ago
    by Gopal Amlekar
  • Answered

    D-side prefetch Cortex-A8 0

    • Cortex-A9
    • Cortex-A
    • Cortex-A8
    5641 views
    2 replies
    Latest over 10 years ago
    by Andreas Hauser
  • Not Answered

    where can I find the detailed explanation of ARM PMU events? 0

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    6966 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    hi. i wonder AMBA 3.0 AXI handshake 0

    • AMBA
    • AXI3
    • AXI
    10067 views
    2 replies
    Latest over 10 years ago
    by In-Gyu.Lee
  • Not Answered

    Minimum MMU table size on ARMv8 to map 4GB memory space, in AArch64 mode 0

    • Cortex-A9
    • AArch64
    • Armv8-A
    • Cortex-A
    • Cortex-A7
    • Cortex-A8
    4446 views
    1 reply
    Latest over 10 years ago
    by yifanfeng
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone