I am doing my PhD in Computer engineering and have developed a processor which is similar to ARM Cortex M0. I have got the obfuscated code and tried to make the comparisons. I was wondering if anyone could give me the details on the area, speed and power of the Cortex M0. This would be of a great help. Thanks a lot in advance.
Hello dr.indira,
had you referred to "Specifications" Tab of Cortex-M0 Processor - ARM ?
There is information about area and power.
Regarding the speed, as far as I know, 16 MHz is the slowest and 96 or 98 MHz are the fastest.
The 16 MHz parts are Toshiba TX00 (M030/M060) and Cypress PSoc4.
The 96 MHz part is Dialog DA14680 (Wearable on Chip).
The 98 MHz part is NuVoton IDS9300.
In addition, what kind information do you want?
Best regards,
Yasuhiko Koumoto.
Uhm, I think that if you can count the LPC43xx as a Cortex-M0, then the speed there is 204 MHz.
I know, it's cheating, but the M0 core can run that fast as far as I remember.
-So it's probably the fastest Cortex-M0 and it's probably also the Cortex-M0 with most memory available (Flash/RAM).
Hello yashuhikoumoto.....Thanks a lot for the reply. The speed part helps a lot..... On the area though, the ARM website says they use around 12,000 gates. Using this along with the obfuscated code information, I calculated the number of transistors to be around 72000 - 100,000. Can you please confirm if you know the actual transistor count?
Also, if this count is true, the floor planned area that is given in the specifications as 0.04mm2 seems to be just the transistors area without considering the wiring.
Just wanted to confirm if the area in the specifications is the area of the core Cortex M0?
Thanks a lot in advance
Hello jensbauer,
thank you for your compensation. I forgot the dual core configuration parts.
regarding the transistor counts, I cannot confirm it because I have no more information.The transistor counts depend on the library and I don't know it.I think the area includes wiring and it is the real (or logical) result when produced by TSMC process.Also it is only the Cortex-M0 area.
Best regards,Yasuhiko Koumoto.
Hi,
Gate count is based on the silicon area of a layout / area of a standard NAND2 gate.
You cannot get the exact gate count by counting the logic operations in the design because synthesis process can easily change the logic structure and compound gates exist for all standard libraries. As a result, your estimation of 72000 to 100000 is completely off
Without going into details, some of the low cost Cortex-M0 microcontrollers on the market has less than 50K gates and that included bus system, peripehrals, and possibly DMA support, etc (exclude memory area and analog components). The 12K gate number is based on minimum configuration at 180ULL process. However, you can get different gate count using different processes, some gives better figure and some give larger areas. For the Cortex-M0 DesignStart, as it has got 16 interrupts and the SysTick timer, the area would be a bit larger than 12K.
If you need further help, you can contact ARM univerity programme and maybe they can give you more information.
regards,
Joseph
HI, I think thats why they call it "obfuscated" code. I have also tried synthesizing on a FPGA and it was not small. I don't have the exact LUT/FF count now. But I can recreate it for you maybe next week.
I think ARM has put in a lot of hardwork in the design and implementation point of view. There must be plenty of optimizations and work done in the datapath itself like the barrel shifter, conditional execution etc. i was told that the Cortex M0 part of the AUP is only functionally equivalent and may not be even cycle accurate (yet to verify). But for sure it is bulkier than the original.
I am curious to know what you are aiming by recreating CortexM0 as part of your PhD work! It would be beneficial to work on specific problems like toggle count, low power techniques, optimization etc.
Hello,
Thanks a lot for the reply and sorry for the late response. We are recreating the ARM M0 using a completely different technology with no logic gates being used and using multi value. Wanted to make a comparison between ours and the actual M0. Any help in giving the details on the synthesized M0 would be greatly appreciated.