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MRS/MSR (Banked register)

Juha Aaltonen

What can be accessed by MRS/MSR in user mode?

In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

B9.3.10      MSR (Banked register)
cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0) (0) (0) (0)

Is this instruction available in ARMv7-A, Cortex A7?

If not, what does this bit pattern do in Cortex A7? UNPREDICTABLE?

There is no explanation of the M1 or M fields in ARMv7-A/R ARM, but in ARMv8 ARM there is.

The instruction encodings look the same, but what kind of mode restrictions apply?

I guess one can't access SP_fig in user mode?

I believe the encoding is the same in both v7-A/R and v8?

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