Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3582 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    SOC for DVBC +1

    4636 views
    2 replies
    Latest over 8 years ago
    by Mellingen_CH
  • Answered

    Software interrupt generation on Cortex M33. +1

    • Cortex-M
    • Cortex-M33
    6979 views
    3 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    Is Cache Stashing introduced in DynamIQ similar to IO coherency? 0

    • Cache coherency
    • DynamIQ Shared Unit (DSU)
    7303 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Is it possible the direct device's interrupt assignment to the guest OS instead of being routed by the hypervisor to the guest OS? 0

    • Armv8-A
    • Generic Interrupt Controller
    5655 views
    2 replies
    Latest over 8 years ago
    by Jorge
  • Answered

    CM4: Can processor halt itself by writing DHCSR +1

    • Cortex-M
    • Cortex-M4
    • AHB
    5326 views
    2 replies
    Latest over 8 years ago
    by Vanhealsing
  • Answered

    About watch point debug excption on Cortex-A53 +3

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    12523 views
    6 replies
    Latest over 8 years ago
    by tao.zeng
  • Answered

    [CM4] Best general way to handle a hardfault/lockup 0

    • Armv7 Exception Model
    • Cortex-M
    • Cortex-M4
    8125 views
    3 replies
    Latest over 8 years ago
    by sfoster
  • Suggested Answer

    What is the relationship between UART and printf within retarget? 0

    • Cortex-M3
    • Cortex-M
    8053 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Suggested Answer

    Where to find the execution cycles of Cortex m7 instruction 0

    • Cortex-M0
    • Cortex-M7
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    25429 views
    9 replies
    Latest over 8 years ago
    by tyskin
  • Not Answered

    Intercore interrupts on a53 between EL1 and EL3 0

    • Cortex-A53
    • Cortex-A
    5906 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Cache Allocation Technology 0

    • AArch64
    • Cache
    • Cortex-A
    • Cortex-A8
    • AArch32
    7034 views
    2 replies
    Latest over 8 years ago
    by daith
  • Answered

    how pc is updated during execution of SWI and any simple instruction like mov R1,R15? +1

    • R15 (PC Program Counter)
    • Armv4T
    • Arm7
    • R14 (LR Link Register)
    • Arm Assembly Language (ASM)
    11780 views
    8 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Suggested Answer

    ARM Cortex A8 L2 Cache Flush Invalidate 0

    • Cortex-A
    • Cortex-A8
    9964 views
    5 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Excepted Practice for NS writes after setting M33 SAU.ALLNS 0

    • TrustZone
    • Armv8-M
    • Block
    7109 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Help Choosing a processor +1

    • Cortex-M7
    • Cortex-M
    • Armv8-M
    • C
    2985 views
    1 reply
    Latest over 8 years ago
    by daith
  • Answered

    ABS (absolute value) function +1

    • SIMD and Vector Execution
    6878 views
    1 reply
    Latest over 8 years ago
    by daith
  • Answered

    What does system memory work actually? 0

    • CMSDK
    • Cortex-M
    4931 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    two’s complement 0

    • Armv7-M
    9318 views
    4 replies
    Latest over 8 years ago
    by thewal
  • Answered

    When does ITAdvance() pseudo-function Exactly called ? 0

    • T32 (Thumb)
    3550 views
    2 replies
    Latest over 8 years ago
    by AbdAllah Talaat
  • Not Answered

    L2 cache with cortex-A8 0

    • Cache
    • Cortex-A
    • Cortex-A8
    3331 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone