Hi together,
im am working on a project managing high IRQ/ISR loads. (NXP S32K14x)
On some critical sections i have to suspend global interrupt mechanism (cpsid i) and resume afterwards.
Is it necessary to include a _dsb or _isb instruction after disabling interrupts to inhibit an already fetched branch to an ISR and thus ensure no preemption takes place of a subsequent critical code section?
Kind Regards
Clemens Grünberger
No, memory barrier is not required for this case.
http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/BIHDFBJF.html
regards,
Joseph