Hello all,
Recently I came across this issue for the cortex M4 core.
We are running a freertos application which loads and stores the value of a variable.
For this we are using the atomic functions like atomic_load, atomic_store and atomic_compare_exchange_strong.
Issue :
* The issue is when in the cacheable region, atomic_load and atomic_store works fine.But any atomic read-modify-write operation
(atomic_compare_exchange_strong, fetch_add, etc.) doesn't operate as expected.
* The atomic_load and atomic_store is able to load and store values in the cache region while atomic_compare_exchange_strong is
working only on memory not on cache.
* Are there any restrictions for any atomic read-modify-write operations ?
* Is there some configuration that needs to be done in order to for caching to work with atomics? It seems as if Load-link and Store-Conditionals functions are going around the cache to either DDR or OCRAM.
Thanks,Shrikant
According to the Cortex-M4 RM exclusive access is not bound to a physical address and should work w/ or w/o cache.How do you know the RMW action does not work? Did you check the assembly code of the RMW function?
BTW: No instruction goes to a specific memory area. It is you who puts variables in certain areas.I suggest to read the various manual (Cortex-M4, armv7-m).
Sounds like it is a Cortex-M4 core inside an i.MX6 or i.MX7 device. In this configuration there is indeed a restriction when performing atomic read-modify-write operations.
See https://community.nxp.com/thread/459977