We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi !
I'm struggling a bit to understand the alignment constraints on the physical address we put in TTBR1_EL1. The ARM ARM v8 doesn't give a precise link in TTBR1_EL1 description to where is alignment is defined. For this post, I'm using a 4k granule everywhere.
From what I understand, bits [x-1,0] must be all 0, for x defined like in table
Table D4-25 Translation table entry addresses when using the 4KB translation granule
For exemple, for a T1SZ of 30, to map 16 GiB of memory, x would be 37 - 30 = 7 (4 x 4k pages)
for a T1SZ of 32, to map 4 GiB of memory, x would be 37 - 32 = 5 (1 x 4k pages)
However in the same table, we see that "BaseAddr[PAMax-1: x]:IA[y:30]:0b000" which would suggest that any look starting at level One needs to be 4K page align.
Could someone clarify the situation, and tell me which constraints I have to fullfuly for the value T1SZ of 30 and 32 ?
Best,
V.
I think this is important (DDI 487B.a):
"D7.2.102 TTBR1_EL1, Translation Table Base Register 1 (EL1)...
A translation table must be aligned to the size of the table, except that when using a translation table base address larger than 48 bits the minimum alignment of a table containing fewer than eight entries is 64 bytes."
Thank you for this reference, I just updated my copy of DDI 487 to DDI 487B.b and see if things are clearer
I'm still quite confused: the TTBR1_EL1 documentation you quote seems to state that for a 4 GiB virtual address space (that is 4 L1 Tables), I should align to 4 * 4096 = 16k -> 14 bits, but the same paragraph, at the end, state that the computation of the 'x' value is described before, and according to my understatement should be 37 - 32 = 5...
Anyone can confirm which interpretation is the right one ?
Note that the example "Example D4-1 Effect of an IA width of 35 bits when using the 4KB granule size" seems to go my way: with 35 bits of IA, TxSZ is 64 - 35 = 29 so we are using the first level lookup. So x is 37 - 29 = 8, and the example states that TTBRx_EL must provide bits [47,8]
Nevermind, both are the same, I got confused by the "size of the table"... In the 4 G/ 16 G scenarios, my 1st table are resp 4 and 16 entries, so they are very small, thus the aligment to x =5/12