Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots from SRAM, how Cortex-M3 fetches instructions from SRAM? Do D-BUS or system bus support instruction fetch？
System bus supports instruction fetching, but instruction and vector fetch requests to this bus are registered. This results in additional cycle of latency because instructions fetched from the System bus take two cycles. And fetching via the ICode bus are not registered (back-to-back fetching).